The invention relates to an integrated circuit arrangement in MOS technology with field effect transistors, in which the individual circuit sections, i.e. the blocks, of the integrated circuit arrangement are interconnected by field-effect transistor switches which can be switched by external test signals applied for testing, and each field-effect transistor is connected to ground or to a negative voltage with its substrate connection.
Such circuit arrangements are known per se. The higher the degree of integration, the more important it becomes to test the individual circuit sections during manufacture and for this purpose it has already been proposed in the literature to divide very complex integrated circuits into separate so-called blocks and to provide these blocks with arrangements by means of which the individual blocks can be isolated from each other so as to enable them to be tested individually and independently of each other. Normally, such isolation is achieved by a switch and in circuit arrangements of this type in MOS technology with field-effect transistors this switch may be a field-effect transistor which is arranged accordingly. Literature relating to the theory of this subject may be found in two papers by Ramamoorthy, a paper in "Journal of the Association for Computing Machinery", Vol. 13, no. 2, April 1966, pages 211 to 222 entitled "Analysis of Graphs by Connectivity Considerations" and another article by the same author in "AFIPS Conference Proceedings", 1967, Spring Joint Computer Conference 30, pages 743 to 756, entitled "A structural theory of machine diagnosis". In particular, in the last-mentioned reference, an arrangement is shown in FIGS. 2a and 2b on page 746 and in the right-hand column of the associated description it is demonstrated that a subsystem, i.e. one block, is to be isolated from its adjacent block, and that this is possible only by means of a switch. Further literature on this subject, relating to field-effect transistors in general, can be found in the book by Tietze and Schenk "Halbleiter-Schaltungstechnik", 4th edition 1978, for example pp. 77 et seq.
This is the state of the art on which the invention is based. From the foregoing references it is in principle known how field-effect transistors are to be arranged. Furthermore, it is known from the general literature how an integration in MOS technology is to be realized and thus, in particular, how such test points should be included in circuit arrangements, as is revealed by the two aforementioned references. The invention describes a method which by means of a simple arrangement enables an arbitrary number of so-called input blocks and an arbitrary number of so-called output blocks to be tested individually or in combination, a first test generally not being completely unambiguous and a second test being necessary, which is independent of the first test, but which immediately yields as result whether a fault occurs in a so-called input block or in a so-called output block.
In order to solve such a problem in the case of an integrated circuit arrangement in MOS-technology with field-effect transistors of the type mentioned above, for testing at least two blocks, namely one input block and one output block, independently of each other, according to the invention at least three field-effect transistor-switch groups are connected to a common connection point, which is connected to the supply voltage via a first field-effect transistor of the depletion type, connected as a load resistor, the field-effect transistor-switch groups each comprising two series-connected enhancement-type field-effect transistors.
In a first switch group for testing an input block a second field-effect transistor is connected with its gate connection to the common connection point, with its drain connection both to a first external connection point and via a third field-effect transistor of the depletion type, arranged as a load resistor, to the supply voltage, and with its source connection to the drain connection of a fourth field-effect transistor, whose source connection is connected to ground and whose gate connection is connected to a first control line.
In a second switching group for connecting or disconnecting an input block a fifth field-effect transistor is connected with its drain connection to the common connection point, with its gate connection to the output of the input block, and with its source connection to the drain connection of a sixth field-effect transistor, whose source connection is connected to ground and whose gate connection is connected to a second control line.
In a third group, for testing an output block, the drain connection of a seventh field-effect transistor is connected to the common connection point, its gate is connected to a second external connection point, and its source is connected to the drain connection of an eighth field-effect transistor, whose source connection is connected to ground and whose gate connection is connected to a third control line.
Thus, when the invention is used, the first group is always necessary. The second group is required for connecting or disconnecting an input block. Therefore, it is included as many times as there are input blocks, and the third group, for testing the output block, is included once if only one output block is to be tested. However, if a plurality of output blocks are to be tested, it should be provided as many times as there are output blocks.
The invention offers a very simple circuit arrangement, which can be integrated into the integrated circuit arrangement and which operates via test connections, which test connections may also be so-called internal connections.